Vertical MOSFETs are popular as high voltage, high power transistors due to the ability to provide a thick, low dopant concentration drift layer to achieve a high breakdown voltage in the off state. Typically, the MOSFET includes a highly doped N-type substrate, a thick low dopant concentration N-type drift layer, a P-type body layer formed in the drift layer, an N-type source at the top of the body layer, and a gate separated from the channel region by a thin gate oxide. A source electrode is formed on the top surface, and a drain electrode is formed on the bottom surface. When the gate is sufficiently positive with respect to the source, the channel region of the P-type body between the N-type source and the N-type drift layer inverts to create a conductive path between the source and drain.
In the device's off-state, when the gate is shorted to the source or negative, the drift layer depletes, and high breakdown voltages, such as exceeding 600 volts, can be sustained between the source and drain. However, due to the required low doping of the thick drift layer, the on-resistance suffers. Increasing the doping of the drift layer reduces the on-resistance but lowers the breakdown voltage.
FIG. 1 is a cross-sectional view of a conventional planar vertical DMOS transistor cell 10 in an array of cells. Planar DMOS transistors are widely used in numerous power switching applications due to their ruggedness compared to trench MOSFETs. However, the conventional planar DMOS transistors have a higher specific on-resistance (Rsp), which is the product of on-resistance and active area. It is desirable to have DMOS transistors with reduced Rsp and lower input, output, and transfer capacitances (Ciss, Coss, and Crss) or gate charge (Qg) to reduce the transistor's conduction and switching losses.
The important resistance components in the conventional DMOS structure shown in FIG. 1 arise from the voltage drop along the inversion channel 12 and the JFET region 14 next to the P-well 16 region. When a sufficiently positive voltage is applied to the gate 17, the gate 17 inverts the channel 12. The source electrode 18 contacts the N++ source regions 20 and the P-well 16, via the P+ contact region 22. A dielectric 24 insulates the gate 17 and source electrode 18. When the gate 17 inverts the channel 12, a horizontal current path is formed between the source regions 20 and the low-dopant density N−− drift region 24, and then the current flows vertically through the N−− drift region 24, the N++ substrate 26, and the drain electrode 28. The N−− drift region 24 needs to be relatively thick to have a high breakdown voltage, but the low dopant density and thickness of the N−− drift region 24 increases on-resistance.
The JFET region 14 restricts the current flow, and it is important to minimize the JFET resistance component by using a sufficiently wide P-well spacing (2Y). However, increasing the spacing Y results in an increase in cell pitch and the active area. Therefore, this tradeoff results in a limited improvement in Rsp.
What is needed is a planar, vertical DMOS transistor with a good Rsp and with a smaller surface area, compared to FIG. 1, for increasing cell density. Further, the transistor should have a high breakdown voltage and high switching speed.